Issued Patents 1997
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1997-09-02 |
| 5611071 | Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture | — | 1997-03-11 |
| 5596731 | Single clock bus transfers during burst and non-burst cycles | Mark Bluhm | 1997-01-21 |