Issued Patents 1997
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5619418 | Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized | David Theodore Blaauw, Joseph W. Norton, Larry G. Jones, R. Iris Bahar | 1997-04-08 |