Issued Patents 1997
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5699303 | Semiconductor memory device having controllable supplying capability of internal voltage | Takeshi Hamamoto, Yoshikazu Morooka | 1997-12-16 |
| 5694352 | Semiconductor memory device having layout area of periphery of output pad reduced | Susumu Tanida, Yasuhiko Tsukikawa, Takayuki Miyamoto | 1997-12-02 |
| 5673232 | Semiconductor memory device operating stably under low power supply voltage with low power consumption | — | 1997-09-30 |
| 5673231 | Semiconductor memory device in which leakage current from defective memory cell can be suppressed during standby | — | 1997-09-30 |
| 5668774 | Dynamic semiconductor memory device having fast operation mode and operating with low current consumption | — | 1997-09-16 |
| 5652730 | Semiconductor memory device having hierarchical boosted power-line scheme | Takashi Kono, Mikio Asakura, Hideto Hidaka | 1997-07-29 |
| 5642317 | Semiconductor memory device incorporating a test mechanism | — | 1997-06-24 |
| 5640363 | Semiconductor memory device | Tadaaki Yamauchi, Makiko Aoki | 1997-06-17 |
| 5636163 | Random access memory with a plurality amplifier groups for reading and writing in normal and test modes | Koichiro Mashiko, Kazutami Arimoto, Noriaki Matsumoto, Yoshio Matsuda | 1997-06-03 |
| 5631873 | Semiconductor memory | — | 1997-05-20 |
| 5621348 | Output driver circuit for suppressing noise generation and integrated circuit device for burn-in test | Hideyuki Ozaki | 1997-04-15 |
| 5610550 | Intermediate potential generator stably providing an internal voltage precisely held at a predeterminded intermediate potential level with reduced current consumption | — | 1997-03-11 |
| 5600607 | Semiconductor memory device that can read out data at high speed | Hiroshi Miyamoto | 1997-02-04 |