Issued Patents 1997
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5701090 | Data output circuit with reduced output noise | Masakazu Hirose | 1997-12-23 |
| 5687123 | Semiconductor memory device | Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 1997-11-11 |
| 5668755 | Semiconductor memory device having well region | — | 1997-09-16 |
| 5652730 | Semiconductor memory device having hierarchical boosted power-line scheme | Takashi Kono, Kiyohiro Furutani, Mikio Asakura | 1997-07-29 |
| 5650972 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1997-07-22 |
| 5650975 | Semiconductor memory device having improved hierarchical I/O line pair structure | Kei Hamade, Kenichi Yasuda, Mikio Asakura | 1997-07-22 |
| 5635744 | Semiconductor memory and semiconductor device having SOI structure | Takahiro Tsuruda, Katsuhiro Suma | 1997-06-03 |
| 5610871 | Semiconductor memory device having a hierarchical bit line structure with reduced interference noise | — | 1997-03-11 |
| 5604707 | Semiconductor memory device responsive to hierarchical internal potentials | Shigehiro Kuge, Shigeki Tomishima, Kazutami Arimoto, Takahiro Tsuruda | 1997-02-18 |
| 5602793 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1997-02-11 |
| 5592009 | Semiconductor device having a floating node that can maintain a predetermined potential for long time, a semiconductor memory device having high data maintenance performance, and a method of manufacturing thereof | — | 1997-01-07 |