Issued Patents 1997
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5666506 | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle | James H. Hesson, Jay LeBlanc | 1997-09-09 |
| 5644744 | Superscaler instruction pipeline having boundary identification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-07-01 |
| 5640526 | Superscaler instruction pipeline having boundary indentification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-06-17 |
| 5625787 | Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-04-29 |
| 5625789 | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle | James H. Hesson, Jay LeBlanc, Walter Thomas Esling, Pamela A. Wilcox | 1997-04-29 |
| 5615350 | Apparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatching, issuing and executing multiple instructions in a single processor cycle | James H. Hesson, Jay LeBlanc | 1997-03-25 |