Issued Patents 1997
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5666506 | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle | Jay LeBlanc, Stephen J. Ciavaglia | 1997-09-09 |
| 5636157 | Modular 64-bit integer adder | Steven C. Espy | 1997-06-03 |
| 5625789 | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle | Jay LeBlanc, Stephen J. Ciavaglia, Walter Thomas Esling, Pamela A. Wilcox | 1997-04-29 |
| 5615350 | Apparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatching, issuing and executing multiple instructions in a single processor cycle | Jay LeBlanc, Stephen J. Ciavaglia | 1997-03-25 |