Issued Patents 1997
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5691946 | Row redundancy block architecture | John K. DeBrosse, Toshiaki Kirihata | 1997-11-25 |
| 5619460 | Method of testing a random access memory | Toshiaki Kirihata | 1997-04-08 |
| 5615164 | Latched row decoder for a random access memory | Toshiaki Kirihata | 1997-03-25 |
| 5610867 | DRAM signal margin test method | John K. DeBrosse, Toshiaki Kirihata | 1997-03-11 |
| 5602051 | Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level | John Cronin, John K. DeBrosse | 1997-02-11 |