Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6928540 | Method and system for synchronizing a clock frequency multiplier with a CPU using a serial initialization packet protocol | — | 2005-08-09 |
| 6888071 | Layout structure and method for supporting two different package techniques of CPU | Tsai-Sheng Chen, Shu-Hui Chen | 2005-05-03 |
| 6877102 | Chipset supporting multiple CPU's and layout method thereof | Tsai-Sheng Chen, Shu-Hui Chen | 2005-04-05 |
| 6870250 | Chip package structure having π filter | — | 2005-03-22 |
| 6844620 | Power layout structure of main bridge chip substrate and motherboard | Shu-Hui Chen | 2005-01-18 |
| 6842347 | Data processing system and associated control chip and printed circuit board | — | 2005-01-11 |
| 6836848 | Power management integrated circuit for overriding an internal frequency ID code of a processor and for providing frequency ID value to a bridge chipset | Chia-Hsing Yu | 2004-12-28 |
| 6826635 | Input/output pad with mornitoring ability and operation method thereof | — | 2004-11-30 |
| 6820219 | Integrated testing method for concurrent testing of a number of computer components through software simulation | Hsiang-Chou Huang, Jiin Lai | 2004-11-16 |
| 6813157 | Mother board and computer system capable of flexibly using synchronous dynamic random access memory and double data rate dynamic random access memory | — | 2004-11-02 |
| 6794744 | Layout structure and method for supporting two different package techniques of CPU | Tsai-Sheng Chen, Shu-Hui Chen | 2004-09-21 |
| 6756665 | Integrated circuit package structure with heat dissipating design | — | 2004-06-29 |
| 6745275 | Feedback system for accomodating different memory module loading | — | 2004-06-01 |
| 6738880 | Buffer for varying data access speed and system applying the same | Jiin Lai, Chia-Hsin Chen | 2004-05-18 |
| 6693451 | Input/output buffer capable of supporting a multiple of transmission logic buses | Jincheng Huang, Yuangtsang Liaw | 2004-02-17 |
| 6681286 | Control chipset having dual-definition pins for reducing circuit layout of memory slot | Chia-Hsing Yu | 2004-01-20 |
| 6667634 | Multi-option setting device for a peripheral control chipset | — | 2003-12-23 |
| 6590827 | Clock device for supporting multiplicity of memory module types | Jin-Cheng Huang | 2003-07-08 |
| 6583365 | Conductive pads layout for BGA packaging structure | — | 2003-06-24 |
| 6564300 | Method and system for controlling the memory access operation by central processing unit in a computer system | — | 2003-05-13 |
| 6563338 | Control circuit and chipset on motherboard for saving terminal resistors and method for realizing the same | Ching-Fu Chuang | 2003-05-13 |
| 6554195 | Dual processor adapter card | Lie Chen, Ching-Fu Chuang, Chia-Hsing Yu | 2003-04-29 |
| 6556051 | Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module | Chia-Hsing Yu | 2003-04-29 |
| 6542996 | Method of implementing energy-saving suspend-to-RAM mode | Jang-Lih Hsieh | 2003-04-01 |
| 6528872 | Packaging structure for ball grid array | — | 2003-03-04 |