Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8060676 | Method of hot switching data transfer rate on bus | Chi-Che Tsai, Chih-Kuo Kao | 2011-11-15 |
| 7805567 | Chipset and northbridge with raid access | Chun-Yuan Su, Jiin Lai | 2010-09-28 |
| 7136955 | Expansion adapter supporting both PCI and AGP device functions | Chun-Yuan Su, Jiin Lai, Chi-Che Tsai | 2006-11-14 |
| 7107373 | Method of hot switching data transfer rate on bus | Chi-Che Tsai, Chih-Kuo Kao | 2006-09-12 |
| 7051148 | Data transmission sequencing method associated with briding device and application system | Jiin Lai, Chi-Che Tsai, Wen-Hao Chuang, Chun-Yuan Su | 2006-05-23 |
| 6941398 | Processing method, chip set and controller for supporting message signaled interrupt | Jiin Lai, Sheng-Chang Peng, Min-Hung Chen, Meng-Cheng Ku, Huei-Li Chou | 2005-09-06 |
| 6934789 | Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode | Sheng-Chang Peng, Hsuan-Yi Wang, Chi-Che Tsai | 2005-08-23 |
| 6925517 | Bus for supporting plural signal line configurations and switch method thereof | Sheng-Chang Peng, Chih-Kuo Kao, Chi-Che Tsai | 2005-08-02 |
| 6836829 | Peripheral device interface chip cache and data synchronization method | Chi-Che Tsai, Chen-Ping Yang | 2004-12-28 |
| 6795883 | Method and system for dividing configuration space | — | 2004-09-21 |
| 6721833 | Arbitration of control chipsets in bus transaction | Jiin Lai, Sheng-Chang Peng, Chi-Che Tsai | 2004-04-13 |
| 6718400 | Data accessing system with an access request pipeline and access method thereof | Chen-Ping Yang, Chi-Che Tsai | 2004-04-06 |
| 6694400 | PCI system controller capable of delayed transaction | Jiin Lai, Chen-Ping Yang, Sheng-Chang Peng, Tse-Hsien Wang | 2004-02-17 |
| 6684284 | Control chipset, and data transaction method and signal transmission devices therefor | Jiin Lai, Sheng-Chang Peng, Chi-Che Tsai | 2004-01-27 |
| 6678771 | Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system | Wen-Hao Chuang, Chi-Che Tsai | 2004-01-13 |
| 6622213 | Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions | Chen-Ping Yang, Chi-Che Tsai | 2003-09-16 |
| 6549964 | Delayed transaction method and device used in a PCI system | Jiin Lai, Chen-Ping Yang, Sheng-Chang Peng, Tse-Hsien Wang | 2003-04-15 |
| 6546448 | Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master | Jiin Lai, Chen-Ping Yang, Chi-Che Tsai | 2003-04-08 |