SS

Srivatsan Srinivasan

VS Ventana Micro Systems: 31 patents #2 of 6Top 35%
NM Netlogic Microsystems: 3 patents #60 of 186Top 35%
OP Optum: 3 patents #29 of 357Top 9%
VB Vonage Business: 2 patents #25 of 105Top 25%
UT University Of Texas: 1 patents #37 of 278Top 15%
QU Qualcomm: 1 patents #7,512 of 12,104Top 65%
📍 Lake Stevens, WA: #2 of 225 inventorsTop 1%
🗺 Washington: #1,344 of 76,902 inventorsTop 2%
Overall (All Time): #63,848 of 4,157,543Top 2%
45
Patents All Time

Issued Patents All Time

Showing 26–45 of 45 patents

Patent #TitleCo-InventorsDate
11797673 Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception John G. Favor 2023-10-24
11734426 Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location John G. Favor 2023-08-22
11733972 Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address John G. Favor 2023-08-22
11687466 Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions John G. Favor 2023-06-27
11625479 Virtually-tagged data cache memory that uses translation context to make entries allocated during execution under one translation context inaccessible during execution under another translation context John G. Favor 2023-04-11
11620377 Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context John G. Favor 2023-04-04
11481332 Write combining using physical address proxies stored in a write combine buffer John G. Favor 2022-10-25
11416400 Hardware cache coherency using physical address proxies John G. Favor 2022-08-16
11416406 Store-to-load forwarding using physical address proxies stored in store queue entries John G. Favor 2022-08-16
11397686 Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries John G. Favor 2022-07-26
11372693 Processing a query having calls to multiple data sources Iddo Gino, Andrey Bukati 2022-06-28
11218590 Systems and methods for providing call verification Shay Ben Yacov, Iliya Barenboim, Romi Gubes, Itay Bianco 2022-01-04
10999413 Public and private API hub synchronization Iddo Gino, Andrey Bukati 2021-05-04
10824483 Application programming interface scoring, ranking and selection Iddo Gino, Andrey Bukati 2020-11-03
10110740 Systems and methods for providing call verification Shay Ben Yacov, Iliya Barenboim, Romi Gubes, Itay Bianco 2018-10-23
8762561 System, method or apparatus for combining multiple streams of media data Nidish Ramachandra Kamath, Prajakt Kulkarni, Robert J. Vachon, Satish Goverdhan, Alex Jong 2014-06-24
8285974 Age matrix for queue entries dispatch order Gaurav Singh, Lintsung Wong 2012-10-09
7840783 System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths Gaurav Singh, Ricardo Ramirez, Wei-Hsiang Chen, Hai Ngoc Nguyen 2010-11-23
7711935 Universal branch identifier for invalidation of speculative instructions Gaurav Singh, Ricardo Ramirez, Wei-Hsiang Chen, Hai Ngoc Nguyen 2010-05-04
7107434 System, method and apparatus for allocating hardware resources using pseudorandom sequences Lizy Kurian John 2006-09-12