Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10734247 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2020-08-04 |
| 10600741 | Semiconductor package with plated metal shielding and a method thereof | Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul | 2020-03-24 |
| 10361146 | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same | Saravuth Sirinorakul, Keith M. Edwards, Albert Loh | 2019-07-23 |
| 10325782 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2019-06-18 |
| 10276477 | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same | Saravuth Sirinorakul, Keith M. Edwards, Albert Loh | 2019-04-30 |
| 10269686 | Method of improving adhesion between molding compounds and an apparatus thereof | Saravuth Sirinorakul | 2019-04-23 |
| 10242953 | Semiconductor package with plated metal shielding and a method thereof | Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul | 2019-03-26 |
| 10163658 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2018-12-25 |
| 10096490 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2018-10-09 |
| 10032645 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2018-07-24 |
| 9922843 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2018-03-20 |
| 9917038 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2018-03-13 |
| 9805955 | Semiconductor package with multiple molding routing layers and a method of manufacturing the same | Saravuth Sirinorakul | 2017-10-31 |
| 9449900 | Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow | Saravuth Sirinorakul | 2016-09-20 |
| 9029198 | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections | Saravuth Sirinorakul | 2015-05-12 |
| 9000590 | Protruding terminals with internal routing interconnections semiconductor device | Saravuth Sirinorakul | 2015-04-07 |