Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9276564 | Noise-assisted reprogrammable nanomechanical logic gate and method | William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego N. Guerra | 2016-03-01 |
| 8436637 | Noise-assisted reprogrammable nanomechanical logic gate and method | William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego N. Guerra | 2013-05-07 |
| 8091062 | Logic circuits having dynamically configurable logic gate arrays | William L. Ditto, Sudeshna Sinha | 2012-01-03 |
| 7973566 | Logic based on the evolution of nonlinear dynamical systems | William L. Ditto, Sudeshna Sinha, Abraham Miliotis | 2011-07-05 |
| 7924059 | Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise | William L. Ditto, Sudeshna Sinha, Adi R. Bulsara | 2011-04-12 |
| 7863937 | Logic based on the evolution of nonlinear dynamical systems | William L. Ditto, Sudeshna Sinha, Abraham Miliotis | 2011-01-04 |
| 7787352 | Method for processing a MEMS/CMOS cantilever based memory storage device | Eyal Bar-Sadeh, Tsung-Kuan A. Chou, Valluri Rao | 2010-08-31 |
| 7415683 | Method and apparatus for a chaotic computing module | William L. Ditto, Sudeshna Sinha | 2008-08-19 |
| 7354788 | Method for processing a MEMS/CMOS cantilever based memory storage device | Eyal Bar-Sadeh, Tsung-Kuan A. Chou, Valluri Rao | 2008-04-08 |
| 7096437 | Method and apparatus for a chaotic computing module using threshold reference signal implementation | William L. Ditto, Sudeshna Sinha | 2006-08-22 |
| 7050320 | MEMS probe based memory | Stefan Lai, Albert Fazio, Valluri Rao, Mike Brown | 2006-05-23 |
| 5242864 | Polyimide process for protecting integrated circuits | Maxine Fassberg, Melton C. Bost, Peter K. Charvat, Lynn A. Price, Robert Lindstedt | 1993-09-07 |