Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11515307 | Heterogeneously integrated semiconductor device and manufacturing method thereof | Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Jen-Inn Chyi, Meng-Yang Chen +3 more | 2022-11-29 |
| 10727231 | Heterogeneously integrated semiconductor device and manufacturing method thereof | Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Jen-Inn Chyi, Meng-Yang Chen +3 more | 2020-07-28 |
| 10446694 | Field-effect transistor structure having two-dimensional transition metal dichalcogenide | Kai-Shin Li, Bo-Wei Wu, Min-Cheng Chen, Jia-Min Shieh | 2019-10-15 |
| 10217500 | Inductive spin-orbit torque device and method for fabricating the same | Yann-Wen Lan, Qiming Shao, Guoqiang Yu, Kang L. Wang | 2019-02-26 |
| 10180509 | Environment monitoring system and vibration sensing device | Yung-Bin Lin, Yu-Sheng Lai, Meng-Huang Gu, Ho-Min Chang, Kuo-Chun Chang +4 more | 2019-01-15 |
| 10134735 | Heterogeneously integrated semiconductor device and manufacturing method thereof | Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Jen-Inn Chyi, Meng-Yang Chen +3 more | 2018-11-20 |
| 6548360 | Electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the same | Chiu-Tsung Huang, Lu Liu | 2003-04-15 |
| 6509218 | Front stage process of a fully depleted silicon-on-insulator device | Hua-Chou Tseng, Jiann Liu | 2003-01-21 |
| 6476448 | Front stage process of a fully depleted silicon-on-insulator device and a structure thereof | Hua-Chou Tseng, Jiann Liu | 2002-11-05 |
| 6455913 | Copper fuse for integrated circuit | Chih-Yung Lin | 2002-09-24 |
| 6451675 | Semiconductor device having varied dopant density regions | Jih-Wen Chou | 2002-09-17 |
| 6376882 | Electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the same | Chiu-Tsung Huang, Lu Liu | 2002-04-23 |
| 6365468 | Method for forming doped p-type gate with anti-reflection layer | Tony Lin, Chih-Yung Lin | 2002-04-02 |
| 6323073 | Method for forming doped regions on an SOI device | Hua-Chou Tseng, Jiann Liu | 2001-11-27 |
| 6319807 | Method for forming a semiconductor device by using reverse-offset spacer process | Tony Lin | 2001-11-20 |
| 6306701 | Self-aligned contact process | — | 2001-10-23 |
| 6294834 | Structure of combined passive elements and logic circuit on a silicon on insulator wafer | Chih-Yung Lin | 2001-09-25 |
| 6281134 | Method for combining logic circuit and capacitor | Wen-Jeng Lin | 2001-08-28 |
| 6277699 | Method for forming a metal-oxide-semiconductor transistor | Coming Chen, Jih-Wen Chou | 2001-08-21 |
| 6274448 | Method of suppressing junction capacitance of source/drain regions | Tony Lin, Jih-Wen Chou | 2001-08-14 |
| 6211023 | Method for fabricating a metal-oxide semiconductor transistor | Jih-Wen Chou | 2001-04-03 |
| 6200870 | Method for forming gate | Tony Lin, Jih-Wen Chou | 2001-03-13 |
| 6197642 | Method for manufacturing gate terminal | Heng-Sheng Huang | 2001-03-06 |
| 6180514 | Method for forming interconnect using dual damascene | Wen-Jeng Lin | 2001-01-30 |
| 6177336 | Method for fabricating a metal-oxide semiconductor device | Tony Lin, Coming Chen, Jih-Wen Chou | 2001-01-23 |