JL

Jengping Lin

UM United Microelectronics: 12 patents #493 of 4,560Top 15%
NT Nanya Technology: 2 patents #292 of 775Top 40%
Overall (All Time): #328,054 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6303491 Method for fabricating self-aligned contact hole Tzu-Ching Tsai, Lin-Chin Su, Tse-Yao Huang 2001-10-16
6215546 Method of optical correction for improving the pattern shrinkage caused by scattering of the light Ronfu Chu, Quentin Chen, Chungwei Hsu 2001-04-10
6107175 Method of fabricating self-aligned contact Han-Chung Lin, Sun-Chieh Chien 2000-08-22
5966604 Method of manufacturing MOS components having lightly doped drain structures Han-Chung Lin, Sun-Chieh Chien 1999-10-12
5679602 Method of forming MOSFET devices with heavily doped local channel stops Sun-Chieh Chien 1997-10-21
5663586 Fet device with double spacer 1997-09-02
5652160 Method of fabricating a buried contact structure with WSi.sub.x sidewall spacers Sun-Chieh Chien 1997-07-29
5641698 Method of fabricating FET device with double spacer 1997-06-24
5612239 Use of oxide spacers formed by liquid phase deposition Sun-Chieh Chien 1997-03-18
5550079 Method for fabricating silicide shunt of dual-gate CMOS device 1996-08-27
5550074 Process for fabricating MOS transistors having anti-punchthrough implant regions formed by the use of a phase-shift mask 1996-08-27
5547900 Method of fabricating a self-aligned contact using a liquid-phase oxide-deposition process 1996-08-20
5510279 Method of fabricating an asymmetric lightly doped drain transistor device Sun-Chieh Chien, Chen-Chiu Hsue 1996-04-23
5504038 Method for selective tungsten sidewall and bottom contact formation Sun-Chieh Chien 1996-04-02
5502009 Method for fabricating gate oxide layers of different thicknesses 1996-03-26