Issued Patents All Time
Showing 51–75 of 222 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6037227 | Method of making high density mask ROM having a two level bit line | — | 2000-03-14 |
| 6030882 | Method for manufacturing shallow trench isolation structure | — | 2000-02-29 |
| 6025229 | Method of fabricating split-gate source side injection flash memory array | — | 2000-02-15 |
| 6017796 | Method of fabricating flash electrically-erasable and programmable read-only memory (EEPROM) device | Hwi-Huang Chen | 2000-01-25 |
| 6008522 | Structure of buried bit line | Yau-Kae Sheu, Wenchi Ting | 1999-12-28 |
| 6008089 | Method of fabricating a split gate flash memory device | — | 1999-12-28 |
| 6001707 | Method for forming shallow trench isolation structure | Chih-Hung Lin | 1999-12-14 |
| 5994185 | Method of fabricating flash memory cell | Yau-Kae Sheu | 1999-11-30 |
| 5994745 | ROM device having shaped gate electrodes and corresponding code implants | — | 1999-11-30 |
| 5976977 | Process for DRAM capacitor formation | — | 1999-11-02 |
| 5976935 | Method of fabricating an electrically erasable and programmable read-only memory (EEPROM) with improved quality for the tunneling oxide layer therein | Ying-Jen Lin, Joe Ko | 1999-11-02 |
| 5972752 | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile | — | 1999-10-26 |
| 5970364 | Method of nitride-sealed oxide-buffered local oxidation of silicon | Hsiu-Wen Huang | 1999-10-19 |
| 5969384 | Flash memory having separate data programming and erasing terminals | — | 1999-10-19 |
| 5966600 | DRAM process with a multilayer stack structure | — | 1999-10-12 |
| 5960288 | Method of fabricating electrostatic discharge protection device | Joe Ko | 1999-09-28 |
| 5960285 | Flash EEPROM device | — | 1999-09-28 |
| 5952039 | Method for manufacturing DRAM capacitor | — | 1999-09-14 |
| 5940703 | Method for manufacturing DRAM capacitors with T-shape lower electrodes by etching oxide sidewalls | — | 1999-08-17 |
| 5932910 | Flash memory cell structure having electrically isolated stacked gate | — | 1999-08-03 |
| 5933722 | Method for manufacturing well structure in integrated circuit | — | 1999-08-03 |
| 5912487 | Split gate flash EEPROM memory cell structure | — | 1999-06-15 |
| 5902124 | DRAM process | — | 1999-05-11 |
| 5899719 | Sub-micron MOSFET | — | 1999-05-04 |
| 5899718 | Method for fabricating flash memory cells | Hwi-Huang Chen, Joe Ko | 1999-05-04 |