JS

Joseph E. Suarez

UA US Army: 1 patents #2,720 of 6,974Top 40%
IBM: 1 patents #44,794 of 70,183Top 65%
📍 South Burlington, VT: #595 of 1,136 inventorsTop 55%
🗺 Vermont: #2,192 of 4,968 inventorsTop 45%
Overall (All Time): #2,278,813 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5517127 Additive structure and method for testing semiconductor wire bond dies Richard J. Bergeron, Thomas Lamothe, John A. Thompson 1996-05-14
5055169 Method of making mixed metal oxide coated substrates Vincent F. Hock, John H. Givens, James M. Rigsbee 1991-10-08