Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12032440 | Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory | David Foley | 2024-07-09 |
| 11663095 | Error detection circuit | Srinivasa Chakravarthy Bs | 2023-05-30 |
| 11593110 | Instruction packing scheme for VLIW CPU architecture | Venkatesh Natarajan, Alexander Tessarolo | 2023-02-28 |
| 11392455 | Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory | David Foley | 2022-07-19 |
| 11061783 | Error detection circuit | Srinivasa Chakravarthy Bs | 2021-07-13 |
| 10177747 | High resolution capture | Alexander Tessarolo | 2019-01-08 |
| 10062451 | Background memory test apparatus and methods | Prasanth Viswanathan Pillai | 2018-08-28 |
| 9910803 | Multi master arbitration scheme in a system on chip | — | 2018-03-06 |
| 9645964 | System and method for improving ECC enabled memory timing | — | 2017-05-09 |
| 9021170 | System and method for improving ECC enabled memory timing | — | 2015-04-28 |
| 9003260 | Partial-writes to ECC (error check code) enabled memories | Padmini Sampath | 2015-04-07 |
| 8803554 | Missing clock circuit switching clock from second to first clock | — | 2014-08-12 |
| 8473797 | Circuits and methods for clock malfunction detection | Chirag Gupta, Padmini Sampath | 2013-06-25 |
| 8384435 | Clock switching circuit with priority multiplexer | — | 2013-02-26 |
| 8384440 | High resolution capture | Alexander Tessarolo | 2013-02-26 |