Issued Patents All Time
Showing 26–50 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11846673 | Device testing architecture, method, and system | — | 2023-12-19 |
| 11835581 | Interposer circuit | — | 2023-12-05 |
| 11835578 | Selectable JTAG or trace access with data store and output | — | 2023-12-05 |
| 11835573 | TSV testing method and apparatus | — | 2023-12-05 |
| 11808810 | AT-speed test access port operations | — | 2023-11-07 |
| 11782091 | Wafer scale testing using a 2 signal JTAG interface | — | 2023-10-10 |
| 11768238 | Integrated circuit with reduced signaling interface | — | 2023-09-26 |
| 11762014 | 3D TAP and scan port architectures | — | 2023-09-19 |
| 11747397 | Addressable test access port apparatus | — | 2023-09-05 |
| 11740286 | Scan testing using scan frames with embedded commands | — | 2023-08-29 |
| 11726135 | Integrated circuit die test architecture | — | 2023-08-15 |
| 11693055 | Direct scan access JTAG | — | 2023-07-04 |
| 11680985 | Falling clock edge JTAG bus routers | — | 2023-06-20 |
| 11680981 | Test access port with address and command capability | — | 2023-06-20 |
| 11675007 | 3D stacked die test architecture | — | 2023-06-13 |
| 11656278 | Apparatus for device access port selection | — | 2023-05-23 |
| 11644503 | TSV testing using test circuits and grounding means | Baher Haroun | 2023-05-09 |
| 11644482 | Testing interposer method and apparatus | — | 2023-05-09 |
| 11639963 | Test compression in a JTAG daisy-chain environment | — | 2023-05-02 |
| 11635464 | Scan frame based test access mechanisms | — | 2023-04-25 |
| 11630151 | Interface to full and reduced pin JTAG devices | — | 2023-04-18 |
| 11609269 | Device testing architecture of an integrated circuit | — | 2023-03-21 |
| 11604222 | Commanded JTAG test access port operations | — | 2023-03-14 |
| 11585852 | At-speed test access port operations | — | 2023-02-21 |
| 11585851 | IEEE 1149.1 interposer apparatus | — | 2023-02-21 |