Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5995748 | Three input arithmetic logic unit with shifter and/or mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-11-30 |
| 5995747 | Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-11-30 |
| 5974539 | Three input arithmetic logic unit with shifter and mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-10-26 |
| 5961635 | Three input arithmetic logic unit with barrel rotator and mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-10-05 |
| 5933624 | Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors while one processor services an interrupt | — | 1999-08-03 |
| 5922070 | Pipelined data processing including program counter recycling | Gary L. Swoboda, Mark R. Hammes, Douglas E. Deao, Nick Ing-Simmons | 1999-07-13 |
| 5881272 | Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor | — | 1999-03-09 |
| 5809288 | Synchronized MIMD multi-processing system and method inhibiting instruction fetch on memory access stall | — | 1998-09-15 |
| 5805913 | Arithmetic logic unit with conditional register source selection | Karl M. Guttag | 1998-09-08 |
| 5768609 | Reduced area of crossbar and method of operation | Robert J. Gove, Nicholas Ing-Simmons, Karl M. Guttag | 1998-06-16 |
| 5761726 | Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1998-06-02 |
| 5758195 | Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register | — | 1998-05-26 |
| 5742538 | Long instruction word controlling plural independent processor operations | Karl M. Guttag, Christopher Jensen Read | 1998-04-21 |
| 5734880 | Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1998-03-31 |
| 5724599 | Message passing and blast interrupt from processor | Karl M. Guttag, Robert J. Gove, Nicholas Ing-Simmons, Iain Robertson | 1998-03-03 |
| 5724566 | Pipelined data processing including interrupts | Gary L. Swoboda, Mark R. Hammes, Douglas E. Deao, Nick Ing-Simmons | 1998-03-03 |
| 5715419 | Data communications system with address remapping for expanded external memory access | Andre Szczepanek, Philip Moyse, Denis Beaudoin | 1998-02-03 |
| 5712999 | Address generator employing selective merge of two independent addresses | Karl M. Guttag | 1998-01-27 |
| 5696959 | Memory store from a selected one of a register pair conditional upon the state of a selected status bit | Karl M. Guttag, Sydney W. Poland | 1997-12-09 |
| 5696913 | Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor | Robert J. Gove, Karl M. Guttag, Nicholas Ing-Simmons | 1997-12-09 |
| 5696954 | Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-12-09 |
| 5651127 | Guided transfers with variable stepping | Robert J. Gove, Karl M. Guttag, Christopher Jensen Read, Iain Robertson, Nicholas Ing Simmons | 1997-07-22 |
| 5640578 | Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section | Nicholas Ing-Simmons, Karl M. Guttag, Robert J. Gove, Jeremiah E. Golston, Christopher Jensen Read +1 more | 1997-06-17 |
| 5634065 | Three input arithmetic logic unit with controllable shifter and mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-05-27 |
| 5613146 | Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors | Robert J. Gove, Nicholas Ing-Simmons, Karl M. Guttag | 1997-03-18 |