Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7167350 | Design implementation to suppress latchup in voltage tolerant circuits | Charvaka Duvvury, Roger A. Cline, Jose A. Cadena-Hernandez | 2007-01-23 |
| 6636067 | Method of testing for micro latch-up | — | 2003-10-21 |