Issued Patents All Time
Showing 51–75 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6222216 | Non-volatile and memory fabricated using a dynamic memory process and method therefor | Wayland Bart Holland | 2001-04-24 |
| 6173356 | Multi-port DRAM with integrated SRAM and systems and methods using the same | — | 2001-01-09 |
| 6041389 | Memory architecture using content addressable memory, and systems and methods using the same | — | 2000-03-21 |
| 6018793 | Single chip controller-memory device including feature-selectable bank I/O and architecture and methods suitable for implementing the same | — | 2000-01-25 |
| 6005799 | Methods and circuits for single-memory dynamic cell multivalue data storage | — | 1999-12-21 |
| 5982696 | Memories with programmable address decoding and systems and methods using the same | — | 1999-11-09 |
| 5963468 | Low latency memories and systems using the same | — | 1999-10-05 |
| 5953738 | DRAM with integral SRAM and arithmetic-logic units | — | 1999-09-14 |
| 5950219 | Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same | — | 1999-09-07 |
| 5926428 | Memories, systems, and methods using precision sense amplifiers | — | 1999-07-20 |
| 5920885 | Dynamic random access memory with a normal precharge mode and a priority precharge mode | — | 1999-07-06 |
| 5912853 | Precision sense amplifiers and memories, systems and methods using the same | — | 1999-06-15 |
| 5861767 | Digital step generators and circuits, systems and methods using the same | Kirit B. Patel | 1999-01-19 |
| 5856940 | Low latency DRAM cell and method therefor | — | 1999-01-05 |
| 5835932 | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM | — | 1998-11-10 |
| 5829016 | Memory system with multiplexed input-output port and systems and methods using the same | Sudhir Sharma, Ronald T. Taylor, Michael E. Runas | 1998-10-27 |
| 5761694 | Multi-bank memory system and method having addresses switched between the row and column decoders in different banks | — | 1998-06-02 |
| 5745428 | Pipelined address memories, and systems and methods using the same | — | 1998-04-28 |
| 5701143 | Circuits, systems and methods for improving row select speed in a row select memory device | — | 1997-12-23 |
| 5687132 | Multiple-bank memory architecture and systems and methods using the same | — | 1997-11-11 |
| 5657281 | Systems and methods for implementing inter-device cell replacements | — | 1997-08-12 |
| 5657285 | Pipelined address memories, and systems and methods using the same | — | 1997-08-12 |
| 5654932 | Memory devices with selectable access type and methods using the same | — | 1997-08-05 |
| 5636174 | Fast cycle time-low latency dynamic random access memories and systems and methods using the same | — | 1997-06-03 |
| 5600606 | Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same | — | 1997-02-04 |