Issued Patents All Time
Showing 51–75 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8921896 | Integrated circuit including linear gate electrode structures having different extension distances beyond contact | Scott T. Becker | 2014-12-30 |
| 8863063 | Finfet transistor circuit | Scott T. Becker, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt +1 more | 2014-10-14 |
| 8839175 | Scalable meta-data objects | Daryl Fox, Jonathan R. Quandt, Scott T. Becker | 2014-09-16 |
| 8823062 | Integrated circuit with offset line end spacings in linear gate electrode level | Scott T. Becker | 2014-09-02 |
| 8759882 | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos | Scott T. Becker | 2014-06-24 |
| 8756551 | Methods for designing semiconductor device with dynamic array section | Scott T. Becker | 2014-06-17 |
| 8680626 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Scott T. Becker | 2014-03-25 |
| 8667443 | Integrated circuit cell library for multiple patterning | Scott T. Becker | 2014-03-04 |
| 8658542 | Coarse grid design methods and structures | Scott T. Becker | 2014-02-25 |
| 8541879 | Super-self-aligned contacts and method for making the same | — | 2013-09-24 |
| 8436400 | Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length | Scott T. Becker | 2013-05-07 |
| 8356268 | Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings | Scott T. Becker | 2013-01-15 |
| 8286107 | Methods and systems for process compensation technique acceleration | Michael A. McAweeney, Scott T. Becker | 2012-10-09 |
| 8283701 | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos | Scott T. Becker | 2012-10-09 |
| 8264008 | Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size | Scott T. Becker | 2012-09-11 |
| 8264009 | Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length | Scott T. Becker | 2012-09-11 |
| 8264007 | Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances | Scott T. Becker | 2012-09-11 |
| 8258551 | Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction | Scott T. Becker | 2012-09-04 |
| 8258548 | Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region | Scott T. Becker | 2012-09-04 |
| 8258547 | Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts | Scott T. Becker | 2012-09-04 |
| 8258550 | Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact | Scott T. Becker | 2012-09-04 |
| 8258549 | Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length | Scott T. Becker | 2012-09-04 |
| 8258552 | Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends | Scott T. Becker | 2012-09-04 |
| 8253172 | Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region | Scott T. Becker | 2012-08-28 |
| 8253173 | Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region | Scott T. Becker | 2012-08-28 |