Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11736594 | Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware | Dhaval Shah, Manoj Karunakaran Nambiar, Mahesh Damodar Barve, Ishtiyaque Shaikh, Piyush Manavar +1 more | 2023-08-22 |
| 11714742 | Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code | Mahesh Damodar Barve, Manoj Karunakara Nambiar, Swapnil RODI | 2023-08-01 |
| 11611638 | Re-assembly middleware in FPGA for processing TCP segments into application layer messages | Dhaval Shah, Manoj Karunakaran Nambiar, Mahesh Damodar Barve, Ishtiyaque Shaikh | 2023-03-21 |
| 11263164 | Multiple field programmable gate array (FPGA) based multi-legged order transaction processing system and method thereof | Mahesh Damodar Barve, Swapnil RODI, Manoj Karunakara Nambiar, Dhaval Shah | 2022-03-01 |
| 11263203 | Systems and methods for storing data in an integrated array and linked list based structure | Mahesh Damodar Barve, Manoj Karunakaran Nambiar, Swapnil RODI | 2022-03-01 |
| 11212218 | Method and system for message based communication and failure recovery for FPGA middleware framework | Manoj Karunakaran Nambiar, Swapnil RODI, Mahesh Damodar Barve | 2021-12-28 |
| 10965519 | Exactly-once transaction semantics for fault tolerant FPGA based transaction systems | Manoj Karunakaran Nambiar, Swapnil RODI, Mahesh Damodar Barve | 2021-03-30 |