Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11621195 | Semiconductor device and method of manufacturing the same | Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao | 2023-04-04 |
| 11569234 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2023-01-31 |
| 11532732 | Multi-gate device and method of fabrication thereof | Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-12-20 |
| 11532725 | Method for forming sidewall spacers and semiconductor devices fabricated thereof | Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2022-12-20 |
| 11527533 | FinFET pitch scaling | Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-12-13 |
| 11495677 | Semiconductor devices and methods of manufacturing thereof | Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-11-08 |
| 11328963 | Multi-gate device and related methods | Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Kuo-Cheng Chiang +1 more | 2022-05-10 |
| 11222794 | Semiconductor fabrication system embedded with effective baking module | Han-Yu Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin | 2022-01-11 |
| 11056393 | Method for FinFET fabrication and structure thereof | Han-Yu Lin, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin +2 more | 2021-07-06 |
| 10950434 | Methods of reducing gate spacer loss during semiconductor manufacturing | Han-Yu Lin, Li-Te Lin, Pinyen Lin | 2021-03-16 |
| 10847633 | Method for forming semiconductor device | Yi-Lun Chen, Fang-Wei Lee, Han-Yu Lin, Li-Te Lin, Pinyen Lin | 2020-11-24 |
| 9076764 | Tunneling transistor with asymmetric gate | Yung-Chun Wu | 2015-07-07 |