Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475742 | Method for forming semiconductor device structure having conductive structure with twin boundaries | Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh +1 more | 2019-11-12 |
| 10283450 | Method for forming semiconductor device structure having conductive structure with twin boundaries | Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh +1 more | 2019-05-07 |
| 9761523 | Interconnect structure with twin boundaries and method for forming the same | Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh +1 more | 2017-09-12 |
| 9023663 | Method for preparing nano-sheet array structure of group V-VI semiconductor | Yu-Lun Chueh, Hung-Wei Tsai | 2015-05-05 |
| 8420185 | Method for forming metal film with twins | Yu-Lun Chueh, Chien-Neng Liao | 2013-04-16 |