Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6297554 | Dual damascene interconnect structure with reduced parasitic capacitance | — | 2001-10-02 |
| 5652172 | Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer | Peng Yung-Sung, An-Min Chiang, Shau-Tsung Yu | 1997-07-29 |