Issued Patents All Time
Showing 226–250 of 719 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11257761 | Logic cell structure and method | Fang Chen, Min-Chang Liang | 2022-02-22 |
| 11251091 | Semiconductor device with contracted isolation feature | Dian-Sheg Yu, Ren-Fen Tsui | 2022-02-15 |
| 11251069 | Method for forming isolation with multi-step structure | Ta-Chun Lin, Tien-Shao CHUANG, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh +1 more | 2022-02-15 |
| 11245005 | Method for manufacturing semiconductor structure with extended contact structure | Ta-Chun Lin, Kuo-Hua Pan, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang +3 more | 2022-02-08 |
| 11239339 | Gate structure and method | Ta-Chun Lin, Kuo-Hua Pan | 2022-02-01 |
| 11239335 | Structure and method for semiconductor devices | — | 2022-02-01 |
| 11222898 | Two-port SRAM structure | — | 2022-01-11 |
| 11210447 | Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices | Jiefeng Lin, Chih-Yung Lin, Dian-Sheg Yu, Hsiao-Lan Yang | 2021-12-28 |
| 11211387 | Fin-based strap cell structure for improving memory performance | — | 2021-12-28 |
| 11201159 | SRAM structure and connection | — | 2021-12-14 |
| 11195760 | Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same | Chun-Hung Chen, Chih-Hung Hsieh | 2021-12-07 |
| 11195937 | Multi-gate transistor structure | — | 2021-12-07 |
| 11189340 | Circuit in memory device for parasitic resistance reduction | Dian-Sheg Yu, Ren-Fen Tsui, Bing-Chian Lin | 2021-11-30 |
| 11171139 | Transistors with various threshold voltages and method for manufacturing the same | — | 2021-11-09 |
| 11171143 | Semiconductor structure with dielectric fin in memory cell and method for forming the same | — | 2021-11-09 |
| 11164746 | Method of manufacturing semiconductor devices and a semiconductor device | Chun-Hung Chen, Chih-Hung Hsieh | 2021-11-02 |
| 11158741 | Nanostructure device and method | — | 2021-10-26 |
| 11158632 | Fin-based strap cell structure for improving memory performance | — | 2021-10-26 |
| 11152488 | Gate-all-around structure with dummy pattern top in channel region and methods of forming the same | Ta-Chun Lin, Kuo-Hua Pan | 2021-10-19 |
| 11145599 | Method of fabricating a memory device having multiple metal interconnect lines | — | 2021-10-12 |
| 11145660 | Dual-port SRAM cell structure | Dian-Sheg Yu, Ren-Fen Tsui, Bing-Chian Lin | 2021-10-12 |
| 11133057 | Memory array with bit-lines connected to different sub-arrays through jumper structures | — | 2021-09-28 |
| 11127742 | Semiconductor device and a method for fabricating the same | Fang Chen, Min-Chang Liang | 2021-09-21 |
| 11127819 | Gate all around transistors for different applications | — | 2021-09-21 |
| 11121234 | Stacked gate spacers | — | 2021-09-14 |