Issued Patents All Time
Showing 326–350 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5821151 | Method of making a capacitor via chemical mechanical polish | — | 1998-10-13 |
| 5821139 | Method for manufacturing a DRAM with increased electrode surface area | — | 1998-10-13 |
| 5817554 | Use of a grated top surface topography for capacitor structures | — | 1998-10-06 |
| 5814526 | Method of forming a DRAM stacked capacitor with a two step ladder storage node | — | 1998-09-29 |
| 5811339 | Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon | — | 1998-09-22 |
| 5807775 | Method for forming a double walled cylindrical capacitor for a DRAM | — | 1998-09-15 |
| 5804481 | Increased capacitor surface area via use of an oxide formation and removal procedure | — | 1998-09-08 |
| 5804480 | method for forming a DRAM capacitor using HSG-Si technique and oxygen implant | Chih-Yuan Lu | 1998-09-08 |
| 5801082 | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits | — | 1998-09-01 |
| 5795806 | Method to increase the area of a stacked capacitor structure by creating a grated top surface bottom electrode | — | 1998-08-18 |
| 5795822 | Method for manufacturing an aligned opening in an integrated circuit | — | 1998-08-18 |
| 5792693 | Method for producing capacitors having increased surface area for dynamic random access memory | — | 1998-08-11 |
| 5792688 | Method to increase the surface area of a storage node electrode, of an STC structure, for DRAM devices, via formation of polysilicon columns | — | 1998-08-11 |
| 5793077 | DRAM trench capacitor with recessed pillar | — | 1998-08-11 |
| 5783486 | Bridge-free self aligned silicide process | — | 1998-07-21 |
| 5783490 | Photolithography alignment mark and manufacturing method | — | 1998-07-21 |
| 5766994 | Dynamic random access memory fabrication method having stacked capacitors with increased capacitance | — | 1998-06-16 |
| 5766993 | Method of fabricating storage node electrode, for DRAM devices, using polymer spacers, to obtain polysilicon columns, with minimum spacing between columns | — | 1998-06-16 |
| 5766998 | Method for fabricating narrow channel field effect transistors having titanium shallow junctions | — | 1998-06-16 |
| 5763304 | Method for manufacturing a capacitor with chemical mechanical polishing | — | 1998-06-09 |
| 5759895 | Method of fabricating a capacitor storage node having a rugged-fin surface | — | 1998-06-02 |
| 5759891 | Increased surface area capacitor via use of a novel reactive ion etch procedure | — | 1998-06-02 |
| 5759894 | Method for forming a DRAM capacitor using HSG-Si | Chih-Yuan Lu | 1998-06-02 |
| 5756384 | Method of fabricating an EPROM cell with a high coupling ratio | — | 1998-05-26 |
| 5753557 | Bridge-free self aligned silicide process | — | 1998-05-19 |