Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11367778 | MOSFET device structure with air-gaps in spacer and methods for forming the same | Po-Jen Wang, Kun-Tsang Chuang | 2022-06-21 |
| 11348944 | Semiconductor wafer with devices having different top layer thicknesses | Kuan-Liang Liu, Wang Po-Jen, Kun-Tsang Chuang, Hsin-Chi Chen | 2022-05-31 |
| 11335638 | Reducing RC delay in semiconductor devices | Kun-Tsang Chuang, Po-Jen Wang | 2022-05-17 |
| 11309268 | Method of designing a layout, method of making a semiconductor structure and semiconductor structure | Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu | 2022-04-19 |
| 11264456 | Isolation regions for reduced junction leakage | Hsin-Chi Chen, Kun-Tsang Chuang | 2022-03-01 |
| 11257902 | SOI device structure for robust isolation | Lin-Chen Lu, Tsung-Han Tsai, Po-Jen Wang | 2022-02-22 |
| 11211283 | Method for forming a bulk semiconductor substrate configured to exhibit soi behavior | Kun-Tsang Chuang, Hsin-Chi Chen | 2021-12-28 |
| 11183570 | Structures and methods for noise isolation in semiconductor devices | Tsung-Han Tsai, Kun-Tsang Chuang | 2021-11-23 |
| 11145539 | Shallow trench isolation for integrated circuits | Hsin-Chi Chen, Kun-Tsang Chuang | 2021-10-12 |
| 11101354 | Method for forming semiconductor device structure with metal silicide layer | Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin | 2021-08-24 |
| 10886165 | Method of forming negatively sloped isolation structures | Tsung-Han Tsai, Kun-Tsang Chuang | 2021-01-05 |
| 10790391 | Source/drain epitaxial layer profile | Hsin-Chi Chen, Kun-Tsang Chuang | 2020-09-29 |
| 10748911 | Integrated circuit for low power SRAM | Shun-Chi TSAI, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo | 2020-08-18 |
| 10734489 | Method for forming semiconductor device structure with metal silicide layer | Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin | 2020-08-04 |
| 10727191 | Semiconductor device with post passivation structure | Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu | 2020-07-28 |
| 10672795 | Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior | Kun-Tsang Chuang, Hsin-Chi Chen | 2020-06-02 |
| 10636870 | Isolation regions for reduced junction leakage | Hsin-Chi Chen, Kun-Tsang Chuang | 2020-04-28 |
| 10636695 | Negatively sloped isolation structures | Tsung-Han Tsai, Kun-Tsang Chuang | 2020-04-28 |
| 10546937 | Structures and methods for noise isolation in semiconductor devices | Tsung-Han Tsai, Kun-Tsang Chuang | 2020-01-28 |
| 10522390 | Shallow trench isolation for integrated circuits | Hsin-Chi Chen, Kun-Tsang Chuang | 2019-12-31 |
| 10163831 | Semiconductor device with post passivation structure and fabrication method therefor | Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu | 2018-12-25 |