Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5962867 | Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures | — | 1999-10-05 |
| 5834346 | Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure | YI SUN, Cheng-Yeh Shih | 1998-11-10 |
| 5757053 | Effective load length increase by topography | — | 1998-05-26 |
| 5736863 | Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures | — | 1998-04-07 |
| 5646057 | Method for a MOS device manufacturing | Jenn Ming Huang, Hsien-Wei Chin, Huan-Chung You, Jang-Cheng Hsieh | 1997-07-08 |
| 5514617 | Method of making a variable resistance polysilicon conductor for an SRAM device | — | 1996-05-07 |
| 5393682 | Method of making tapered poly profile for TFT device manufacturing | — | 1995-02-28 |
| 5254497 | Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit | — | 1993-10-19 |