Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10304945 | High-speed semiconductor device and method for forming the same | Victor Chiang Liang, Chi-Feng Huang, Shu Fang Fu | 2019-05-28 |
| 10290725 | Bipolar junction transistor and integrated circuit device | Chung-Hao Chu, Chi-Feng Huang, Victor Chiang Liang | 2019-05-14 |
| 10269658 | Integrated circuit devices with well regions and methods for forming the same | Chi-Feng Huang, Victor Chiang Liang, Mingo Liu | 2019-04-23 |
| 10170571 | Semiconductor device and manufacturing method thereof | Chi-Feng Huang, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo | 2019-01-01 |
| 10157916 | Semiconductor device and manufacturing method thereof | Victor Chiang Liang, Chi-Feng Huang, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu +3 more | 2018-12-18 |
| 10141429 | FinFET having isolation structure and method of forming the same | Fu-Huan Tsai, Feng Yuan | 2018-11-27 |
| 10134868 | MOS devices with mask layers and methods for forming the same | Chu Fu Chen, Chi-Feng Huang, Victor Chiang Liang | 2018-11-20 |
| 9991260 | HVMOS reliability evaluation using bulk resistances as indices | Chi-Feng Huang, Tse-Hua Lu | 2018-06-05 |
| 9947762 | MOS devices with mask layers and methods for forming the same | Chu Fu Chen, Chi-Feng Huang, Victor Chiang Liang | 2018-04-17 |
| 9882012 | Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions | Chi-Feng Huang, Victor Chiang Liang | 2018-01-30 |
| 9824985 | Semiconductor device and semiconductor system | Shuo-Chun Chou, Chi-Feng Huang, Victor Chiang Liang | 2017-11-21 |
| 9825118 | High voltage metal-oxide-metal (HV-MOM) device, HV-MOM layout and method of making the HV-MOM device | Shu Fang Fu, Chang-Sheng Liao | 2017-11-21 |
| 9799753 | FinFET having isolation structure and method of forming the same | Chi-Feng Huang, Victor Chiang Liang | 2017-10-24 |
| 9780211 | Power cell and power cell circuit for a power amplifier | Chewn-Pu Jou, Tzu-Jin Yeh | 2017-10-03 |
| 9780089 | Bipolar junction transistor layout | Han-Min Tsai, Chi-Feng Huang, Victor Chiang Liang, Hsiao-Chun Lee, Shou-Chun Chou +1 more | 2017-10-03 |
| 9772366 | Circuits and methods of testing a device under test using the same | Shuo-Chun Chou, Chi-Feng Huang, Victor Chiang Liang | 2017-09-26 |
| 9761584 | Buried channel semiconductor device and method for manufacturing the same | Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh +2 more | 2017-09-12 |
| 9653542 | FinFET having isolation structure and method of forming the same | Fu-Huan Tsai, Feng Yuan | 2017-05-16 |
| 9633956 | RF switch on high resistive substrate | Chi-Feng Huang, Shu Fang Fu, Tzu-Jin Yeh, Chewn-Pu Jou | 2017-04-25 |
| 9484408 | Bipolar junction transistor layout | Han-Min Tsai, Chi-Feng Huang, Victor Chiang Liang, Hsiao-Chun Lee, Shou-Chun Chou +1 more | 2016-11-01 |
| 9478659 | FinFET having doped region and method of forming the same | Chi-Feng Huang, Victor Chiang Liang | 2016-10-25 |
| 9425154 | Noise decoupling structure with through-substrate vias | Chewn-Pu Jou, Sally Liu | 2016-08-23 |
| 9406672 | Capacitor arrays for minimizing gradient effects and methods of forming the same | Chi-Feng Huang | 2016-08-02 |
| 9406671 | Capacitor arrays for minimizing gradient effects and methods of forming the same | Chi-Feng Huang | 2016-08-02 |
| 9337269 | Buried-channel FinFET device and method | Fu-Huan Tsai, Feng Yuan, Chi-Feng Huang, Victor Chiang Liang | 2016-05-10 |