YR

Yael Rindenau

SY Synopsys: 1 patents #1,143 of 2,302Top 50%
Overall (All Time): #3,582,947 of 4,157,543Top 90%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6237127 Static timing analysis of digital electronic circuits using non-default constraints known as exceptions Ted L. Craven, Denis Baylor 2001-05-22