MR

Martin Ranke

SY Synopsys: 1 patents #1,143 of 2,302Top 50%
Overall (All Time): #4,139,066 of 4,157,543Top 100%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10423742 Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts Qiuyang Wu, Min Li 2019-09-24