Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5333032 | Logic design system and method in the same | Noriko Matsumoto, Shoji Takaoka, Masahiko Ueda | 1994-07-26 |
| 5206825 | Arithmetic processor using signed-digit representation of external operands | Naofumi Takagi, Tsuguyasu Hatsuda, Toru Kakiage, Takashi Taniguchi | 1993-04-27 |
| 5153847 | Arithmetic processor using signed digit representation of internal operands | Naofumi Takagi, Tsuguyasu Hatsuda, Toru Kakiage, Takashi Taniguchi | 1992-10-06 |
| 5146583 | Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof | Masahiko Matsunaka, Masahiko Ueda | 1992-09-08 |
| 5043914 | Circuit transformation system, circuit transformation method, inverted logic generation method, and logic design system | Noriko Matsumoto, Masahiko Ueda, Masahiko Matsunaka | 1991-08-27 |
| 5031136 | Signed-digit arithmetic processing units with binary operands | Shigeo Kuninobu | 1991-07-09 |
| 4942536 | Method of automatic circuit translation | Toshinori Watanabe, Fumihiko Mori, Makoto Furihata, Yasuo Kominami, Noboru Horie | 1990-07-17 |
| 4935892 | Divider and arithmetic processing units using signed digit operands | Shigeo Kuninobu | 1990-06-19 |
| 4878192 | Arithmetic processor and divider using redundant signed digit arithmetic | Shigeo Kuninobu | 1989-10-31 |
| 4873660 | Arithmetic processor using redundant signed digit arithmetic | Shigeo Kuninobu | 1989-10-10 |
| 4868777 | High speed multiplier utilizing signed-digit and carry-save operands | Shigeo Kuninobu, Naofumi Takagi | 1989-09-19 |
| 4866657 | Adder circuitry utilizing redundant signed digit operands | Shigeo Kuninobu, Naofumi Takagi, Takashi Taniguchi | 1989-09-12 |
| 4866655 | Arithmetic processor and divider using redundant signed digit | Shigeo Kuninobu, Naofumi Takagi, Takashi Taniguchi | 1989-09-12 |
| 4864528 | Arithmetic processor and multiplier using redundant signed digit arithmetic | Shigeo Kuninobu, Naofumi Takagi, Takashi Taniguchi | 1989-09-05 |
| 4803636 | Circuit translator | Toshinori Watanabe, Noboru Horie, Makoto Furihata, Yasuo Kominami, Fumihiko Mori | 1989-02-07 |
| 4644480 | Reliability analyzing system for manufacturing processes | Koichi Haruna, Kazuo Nakao, Tsutomu Tashiro, Kuniaki Matsumoto, Nobuyuki Saida | 1987-02-17 |