Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5146583 | Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof | Tamotsu Nishiyama, Masahiko Ueda | 1992-09-08 |
| 5043914 | Circuit transformation system, circuit transformation method, inverted logic generation method, and logic design system | Tamotsu Nishiyama, Noriko Matsumoto, Masahiko Ueda | 1991-08-27 |