Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6802017 | Partial enabling of functional unit based on data and size pair in register | Shuichi Takayama, Masato Suzuki | 2004-10-05 |
| 6606703 | Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions | Shuichi Takayama, Kensuke Odani, Akira Tanaka, Masato Suzuki, Tetsuya Tanaka +2 more | 2003-08-12 |
| 6397319 | Process for executing highly efficient VLIW | Shuichi Takayama | 2002-05-28 |
| 6324639 | Instruction converting apparatus using parallel execution code | Taketo Heishi, Tetsuya Tanaka, Shuishi Takayama, Kensuke Odani | 2001-11-27 |
| 6282632 | Information processor having duplicate operation flags | Tetsuya Tanaka, Shuichi Takayama | 2001-08-28 |
| 6237084 | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing | Toru Morikawa, Akira Miyoshi, Keizo Sumida | 2001-05-22 |
| 6230258 | Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions | Shuichi Takayama, Kensuke Odani, Akira Tanaka, Masato Suzuki, Tetsuya Tanaka +2 more | 2001-05-08 |
| 6219779 | Constant reconstructing processor which supports reductions in code size | Shuichi Takayama, Tetsuya Tanaka, Taketo Heishi, Masato Suzuki | 2001-04-17 |
| 6209080 | Constant reconstruction processor that supports reductions in code size and processing time | Taketo Heishi, Akira Tanaka, Tetsuya Tanaka, Shuichi Takayama, Kensuke Odani +1 more | 2001-03-27 |
| 6195740 | Constant reconstructing processor that execute an instruction using an operand divided between instructions | Taketo Heishi, Akira Tanaka, Tetsuya Tanaka, Shuichi Takayama, Kensuke Odani +1 more | 2001-02-27 |
| 6170998 | Processor which returns from a subroutine at high speed and a program translating apparatus which generates machine programs that makes a high-speed return from a subroutine | Kazushi Yamamoto, Shuichi Takayama, Nobuki Tominaga, Shinya Miyaji | 2001-01-09 |
| 6161171 | Apparatus for pipelining sequential instructions in synchronism with an operation clock | Toru Morikawa, Shinji Ozaki, Keisuke Kaneko, Satoshi Ogura, Masato Suzuki | 2000-12-12 |
| 6085306 | Processor for executing highly efficient VLIW | Shuichi Takayama | 2000-07-04 |
| 6044157 | Microprocessor suitable for reproducing AV data while protecting the AV data from illegal copy and image information processing system using the microprocessor | Yasushi Uesaka, Kazuhiko Yamauchi, Masayuki Kozuka, Koichi Horiuchi, Syusuke Haruna | 2000-03-28 |
| 6018796 | Data processing having a variable number of pipeline stages | Masato Suzuki, Toru Morikawa, Shinya Miyaji | 2000-01-25 |
| 5978905 | Program translating apparatus and a processor which achieve high-speed execution of subroutine branch instructions | Shuichi Takayama, Nobuki Tominaga, Shinya Miyaji, Seiichi Urushibara | 1999-11-02 |
| 5974540 | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing | Toru Morikawa, Akira Miyoshi, Keizo Sumida | 1999-10-26 |
| 5928358 | Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware | Shuichi Takayama | 1999-07-27 |
| 5909565 | Microprocessor system which efficiently shares register data between a main processor and a coprocessor | Toru Morikawa, Shinya Miyaji | 1999-06-01 |
| 5907694 | Data processing apparatus for performing a pipeline operation on a load and extension instruction | Masato Suzuki, Shinya Miyaji, Nobuki Tominaga, Yoshito Nishimichi | 1999-05-25 |
| 5850551 | Compiler and processor for processing loops at high speed | Shuichi Takayama, Nobuki Tominaga, Shinya Miyaji | 1998-12-15 |
| 5847978 | Processor and control method for performing proper saturation operation | Satoshi Ogura, Shinya Miyaji, Masato Suzuki | 1998-12-08 |
| 5796970 | Information processing apparatus for realizing data transfer for a plurality of registers using instructions of short word length | Nobuki Tominaga, Shinya Miyaji, Shuichi Takayama | 1998-08-18 |
| 5758162 | Program translating apparatus and a processor which achieve high-speed execution of subroutine branch instructions | Shuichi Takayama, Nobuki Tominaga, Shinya Miyaji, Seiichi Urushibara | 1998-05-26 |
| 5748970 | Interrupt control device for processing interrupt request signals that are greater than interrupt level signals | Shinya Miyaji | 1998-05-05 |