Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8441865 | Non-volatile memory device with controlled discharge | Giuseppe Castagna | 2013-05-14 |
| 8423701 | Flash memory device with a low pin count (LPC) communication interface | Bruno Calandrino | 2013-04-16 |
| 7519751 | Method of generating an enable signal of a standard memory core and relative memory device | Salvatore Polizzi, Andrea Scavuzzo | 2009-04-14 |
| 7457908 | Integrated memory device with multi-sector selection commands | Salvatore Mazzara, Paolino Schillaci | 2008-11-25 |
| 7376810 | Integrated device with multiple reading and/or writing commands | Salvatore Polizzi, Salvatore Mazzara | 2008-05-20 |
| 7366012 | Synchronous memory device with reduced power consumption | Paolino Schillaci, Salvatore Mazzara | 2008-04-29 |
| 7151705 | Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface | Salvatore Polizzi, Paolino Schillaci | 2006-12-19 |
| 6990596 | Memory device outputting read data in a time starting from a rising edge of an external clock that is shorter than that of known devices | Salvatore Polizzi | 2006-01-24 |
| 6975559 | Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface | Salvatore Polizzi, Salvatore Poli | 2005-12-13 |
| 6927991 | Memory device accessible with different communication protocols | Andrea Scavuzzo, Salvatore Polizzi | 2005-08-09 |
| 6917994 | Device and method for automatically generating an appropriate number of wait cycles while reading a nonvolatile memory | Alessandro Francesco Maone | 2005-07-12 |
| 6894914 | Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol | Salvatore Polizzi | 2005-05-17 |
| 6892269 | Nonvolatile memory device with double serial/parallel communication interface | Salvatore Polizzi, Salvatore Poli | 2005-05-10 |
| 6785174 | Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface | Marco Messina, Salvatore Polizzi | 2004-08-31 |
| 6674666 | Device and method for timing the reading of a nonvolatile memory with reduced switching noise | Alessandro Francesco Maone | 2004-01-06 |