Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923855 | Schmitt trigger with pull-up transistor | Manoj Kumar Tiwari | 2024-03-05 |
| 11522521 | Glitch filter having a switched capacitance and reset stages | Manoj Kumar Tiwari | 2022-12-06 |
| 11075624 | Hybrid driver having low output pad capacitance | Manish Garg | 2021-07-27 |
| 10848147 | High performance I2C transmitter and bus supply independent receiver, supporting large supply voltage variations | Atul DWIVEDI | 2020-11-24 |
| 10454466 | Biasing cascode transistors of an output buffer circuit for operation over a wide range of supply voltages | Manoj Kumar Tiwari | 2019-10-22 |
| 10224922 | Biasing cascode transistor of an output buffer circuit for operation over a wide range of supply voltages | Manoj Kumar Tiwari | 2019-03-05 |
| 9762243 | Apparatus for reference voltage generation for I/O interface circuit | Vinod Kumar | 2017-09-12 |
| 9473135 | Driver circuit including driver transistors with controlled body biasing | Paras Garg, Rajesh Yadav, Ravinder Kumar | 2016-10-18 |
| 9467125 | CMOS Schmitt trigger circuit and associated methods | Vinod Kumar | 2016-10-11 |
| 9397622 | Programmable hysteresis comparator | Sameer Vashishtha | 2016-07-19 |
| 9264045 | Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology | Sameer Vashishtha | 2016-02-16 |
| 8981817 | Operating conditions compensation circuit | Vinod Kumar, Pradeep Kumar Badrathwal, Paras Garg, Kallol Chatterjee, Pierre Dautriche | 2015-03-17 |
| 8531227 | Level shifter | Vinod Kumar | 2013-09-10 |
| 8253437 | Reduction of signal skew | Paras Garg | 2012-08-28 |
| 8207754 | Architecture for efficient usage of IO | Paras Garg | 2012-06-26 |