Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11481315 | Booting an application from multiple memories | Stephan Rosner, Venkat Natarajan | 2022-10-25 |
| 11082449 | Remote memory diagnostics | Wen-Ching Chou, Sandeep Krishnegowda | 2021-08-03 |
| 11010062 | Method for providing read data flow control or error reporting using a read data strobe | Mark Alan McClain, Clifford Alan Zitlaw | 2021-05-18 |
| 10776257 | Booting an application from multiple memories | Stephan Rosner, Venkat Natarajan | 2020-09-15 |
| 10331359 | Memory subsystem with wrapped-to-continuous read | Shinsuke Okada, Yuichi Ise, Kai Dieffenbach, Kiyomatsu Shouji | 2019-06-25 |
| 10120590 | Method for providing read data flow control or error reporting using a read data strobe | Mark Alan McClain, Clifford Alan Zitlaw | 2018-11-06 |
| 10019351 | Booting an application from multiple memories | Stephan Rosner, Venkat Natarajan | 2018-07-10 |
| 9792049 | Memory subsystem with wrapped-to-continuous read | Shinsuke Okada, Yuichi Ise, Kai Dieffenbach, Kiyomatsu Shouji | 2017-10-17 |
| 9600384 | System-on-chip verification | William Chu, Lijun Pan, Hongjun Xue | 2017-03-21 |
| 9477617 | Memory buffering system that improves read/write performance and provides low latency for mobile systems | Stephan Rosner, Roger D. Isaac | 2016-10-25 |
| 9477619 | Programmable latency count to achieve higher memory bandwidth | Dawn Hopper, Clifford Alan Zitlaw | 2016-10-25 |
| 9454421 | Method for providing read data flow control or error reporting using a read data strobe | Mark Alan McClain, Clifford Alan Zitlaw | 2016-09-27 |
| 9142209 | Data pattern analysis | Richard Fastow | 2015-09-22 |
| 9047237 | Power savings apparatus and method for memory device using delay locked loop | Clifford Alan Zitlaw, Stephan Rosner, Sylvain Dubois | 2015-06-02 |
| 8818802 | Real-time data pattern analysis system and method of operation thereof | Richard Fastow | 2014-08-26 |
| 8819326 | Host/client system having a scalable serial bus interface | Stephan Rosner, Jeremy Mah | 2014-08-26 |
| 8700830 | Memory buffering system that improves read/write performance and provides low latency for mobile systems | Stephan Rosner, Roger D. Isaac | 2014-04-15 |
| 8359423 | Using LPDDR1 bus as transport layer to communicate to flash | Stephan Rosner, Roger D. Isaac | 2013-01-22 |
| 8239637 | Byte mask command for memories | Roger D. Isaac, Stephan Rosner, Jeremy Mah | 2012-08-07 |
| 8230154 | Fully associative banking for memory | Roger D. Isaac, Stephan Rosner, Jeremy Mah | 2012-07-24 |
| 8140778 | Apparatus and method for data capture using a read preamble | Clifford Alan Zitlaw, Stephan Rosner, Dubois Sylvain | 2012-03-20 |
| 7840900 | Replacing reset pin in buses while guaranteeing system recovery | Stephan Rosner, Roger D. Isaac | 2010-11-23 |
| 7813459 | Digital data transfer between different clock domains | Stephan Rosner, Jeremy Mah | 2010-10-12 |
| 7644226 | System and method for maintaining RAM command timing across phase-shifted time domains | Roger D. Isaac, Stephan Rosner | 2010-01-05 |
| 7639768 | Method for improving performance in a mobile device | Jeremy Mah, Stephan Rosner | 2009-12-29 |