Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12087858 | Semiconductor device including stress application layer | — | 2024-09-10 |
| 10868177 | Semiconductor device and manufacturing method thereof | — | 2020-12-15 |
| 10854751 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2020-12-01 |
| 10833101 | Three-dimensional memory device with horizontal silicon channels and method of making the same | Shigeki Shimomura, Hiroyuki Ogawa | 2020-11-10 |
| 10748966 | Three-dimensional memory device containing cobalt capped copper lines and method of making the same | Wei-Kuo Shih, Yuji Takahashi | 2020-08-18 |
| 10535769 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2020-01-14 |
| 10381366 | Air gap three-dimensional cross rail memory device and method of making thereof | Yuji Takahashi, Vincent Shih | 2019-08-13 |
| 10269961 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2019-04-23 |
| 10199227 | Method for fabricating a metal high-k gate stack for a buried recessed access device | Mark Fischer, Michael P. Violette | 2019-02-05 |
| 9947790 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2018-04-17 |
| 9876109 | Transistors having strained channel under gate in a recess | Mark Fischer | 2018-01-23 |
| 9680007 | Method for fabricating a metal high-k gate stack for a buried recessed access device | Mark Fischer, Michael P. Violette | 2017-06-13 |
| 9640656 | Transistors having strained channel under gate in a recess | Mark Fischer | 2017-05-02 |
| 9601622 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2017-03-21 |
| 9337305 | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2016-05-10 |
| 9337042 | Method for fabricating a metal high-k gate stack for a buried recessed access device | Mark Fischer, Michael P. Violette | 2016-05-10 |
| 9153663 | Semiconductor device having a stress-inducing layer between channel region and source and drain regions | Hitoshi Wakabayashi | 2015-10-06 |
| 8980713 | Method for fabricating a metal high-k gate stack for a buried recessed access device | Mark Fischer, Michael P. Violette | 2015-03-17 |
| 8896068 | Semiconductor device including source/drain regions and a gate electrode, and having contact portions | — | 2014-11-25 |
| 8779546 | Semiconductor memory system with bit line and method of manufacture thereof | Masanori Tsukamoto | 2014-07-15 |
| 6841472 | Semiconductor device and method of fabricating the same | — | 2005-01-11 |
| 6713333 | Method for fabricating a MOSFET | — | 2004-03-30 |
| 6316836 | Semiconductor device interconnection structure | — | 2001-11-13 |