Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7730366 | Phase error determination method and digital phase-locked loop system | Shinobu Nakamura, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu | 2010-06-01 |
| 7578676 | Semiconductor device | Shunichi Sukegawa, Kenichi Shigenami | 2009-08-25 |
| 7554186 | Semiconductor device | Kenichi Shigenami, Shunichi Sukegawa | 2009-06-30 |
| 7469367 | Phase error determination method and digital phase-locked loop system | Shinobu Nakamura, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu | 2008-12-23 |
| 7351068 | Semiconductor device | Shunichi Sukegawa, Kenichi Shigenami | 2008-04-01 |
| 7342986 | Digital PLL device | Shinobu Nakamura, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu | 2008-03-11 |
| 7315968 | Phase error determination method and digital phase-locked loop system | Shinobu Nakamura, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu | 2008-01-01 |
| 6992958 | Phase-locked loop circuit for reproducing a channel clock | Shinobu Nakamura | 2006-01-31 |