MK

Mark Kennard

ST S.O.I. Tec Silicon On Insulator Technologies: 6 patents #27 of 155Top 20%
Lam Research: 4 patents #662 of 2,128Top 35%
AA Asm America: 2 patents #79 of 181Top 45%
SO Soitec: 2 patents #91 of 259Top 40%
CN CNRS: 1 patents #3,857 of 11,908Top 35%
📍 Pleasanton, CA: #555 of 3,062 inventorsTop 20%
🗺 California: #50,852 of 386,348 inventorsTop 15%
Overall (All Time): #420,704 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
9093271 Method for manufacturing a thick epitaxial layer of gallium nitride on a silicon or similar substrate and layer obtained using said method David Schenk, Alexis Bavard, Yvon Cordier, Eric Frayssinet, Daniel Rondi 2015-07-28
8778777 Method for manufacturing a heterostructure aiming at reducing the tensile stress condition of a donor substrate 2014-07-15
8084784 Semiconductor heterostructure and method for forming same Christophe Figuet 2011-12-27
7825401 Strained layers within semiconductor buffer structures Nyles Wynn Cody, Christophe Figuet 2010-11-02
7772127 Semiconductor heterostructure and method for forming same Christophe Figuet 2010-08-10
7608526 Strained layers within semiconductor buffer structures Nyles Wynn Cody, Christophe Figuet 2009-10-27
7572331 Method of manufacturing a wafer Konstantin Bourdelle, Ian Cayrefourcq 2009-08-11
7407548 Method of manufacturing a wafer Konstantin Bourdelle, Ian Cayrefourcq 2008-08-05
6669783 High temperature electrostatic chuck Greg Sexton, Alan M. Schoepp 2003-12-30
6567258 High temperature electrostatic chuck Greg Sexton, Alan M. Schoepp 2003-05-20
6377437 High temperature electrostatic chuck Greg Sexton, Alan M. Schoepp 2002-04-23
5935874 Techniques for forming trenches in a silicon layer of a substrate in a high density plasma processing system 1999-08-10