Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9886416 | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations | — | 2018-02-06 |
| 9858080 | Method for implementing a reduced size register view data structure in a microprocessor | — | 2018-01-02 |
| 9823939 | System for an instruction set agnostic runtime architecture | — | 2017-11-21 |
| 9823930 | Method for emulating a guest centralized flag architecture by using a native distributed flag architecture | — | 2017-11-21 |
| 9811377 | Method for executing multithreaded instructions grouped into blocks | — | 2017-11-07 |
| 9767038 | Systems and methods for accessing a unified translation lookaside buffer | Karthikeyan Avudaiyappan | 2017-09-19 |
| 9740499 | Method for implementing a line speed interconnect structure | — | 2017-08-22 |
| 9733909 | System converter that implements a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address | — | 2017-08-15 |
| 9733942 | Mapping of guest instruction block assembled according to branch prediction to translated native conversion block | — | 2017-08-15 |
| 9733944 | Instruction sequence buffer to store branches having reliably predictable instruction sequences | — | 2017-08-15 |
| 9720839 | Systems and methods for supporting a plurality of load and store accesses of a cache | Karthikeyan Avudaiyappan | 2017-08-01 |
| 9720831 | Systems and methods for maintaining the coherency of a store coalescing cache and a load cache | Karthikeyan Avudaiyappan | 2017-08-01 |
| 9710387 | Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor | — | 2017-07-18 |
| 9710399 | Systems and methods for flushing a cache with modified data | Karthikeyan Avudaiyappan | 2017-07-18 |
| 9639364 | Guest to native block address mappings and management of native code storage | — | 2017-05-02 |
| 9575762 | Method for populating register view data structure by using register template snapshots | — | 2017-02-21 |
| 9569216 | Method for populating a source view data structure by using register template snapshots | — | 2017-02-14 |
| 9542187 | Guest instruction block with near branching and far branching sequence construction to native instruction block | — | 2017-01-10 |
| 9501280 | Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer | — | 2016-11-22 |
| 9454491 | Systems and methods for accessing a unified translation lookaside buffer | Karthikeyan Avudaiyappan | 2016-09-27 |
| 9442772 | Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines | — | 2016-09-13 |
| 9436476 | Method and apparatus for sorting elements in hardware structures | Mandeep Singh | 2016-09-06 |
| 9430410 | Systems and methods for supporting a plurality of load accesses of a cache in a single cycle | Karthikeyan Avudaiyappan | 2016-08-30 |
| 9424046 | Systems and methods for load canceling in a processor that is connected to an external interconnect fabric | Karthikeyan Avudaiyappan | 2016-08-23 |
| 9348754 | Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher | Karthikeyan Avudaiyappan | 2016-05-24 |