Issued Patents All Time
Showing 1–25 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11281481 | Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture | — | 2022-03-22 |
| 10884739 | Systems and methods for load canceling in a processor that is connected to an external interconnect fabric | Karthikeyan Avudaiyappan | 2021-01-05 |
| 10810014 | Method and apparatus for guest return address stack emulation supporting speculation | — | 2020-10-20 |
| 10713047 | Fast unaligned memory access | Mandeep Singh | 2020-07-14 |
| 10564975 | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines | — | 2020-02-18 |
| 10521239 | Microprocessor accelerated code optimizer | — | 2019-12-31 |
| 10514926 | Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor | — | 2019-12-24 |
| 10503514 | Method for implementing a reduced size register view data structure in a microprocessor | — | 2019-12-10 |
| 10310987 | Systems and methods for accessing a unified translation lookaside buffer | Karthikeyan Avudaiyappan | 2019-06-04 |
| 10303484 | Method for implementing a line speed interconnect structure | — | 2019-05-28 |
| 10289605 | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations | — | 2019-05-14 |
| 10282170 | Method for a stage optimized high speed adder | — | 2019-05-07 |
| 10255076 | Method for performing dual dispatch of blocks and half blocks | — | 2019-04-09 |
| 10228949 | Single cycle multi-branch prediction including shadow cache for early far branch prediction | — | 2019-03-12 |
| 10191746 | Accelerated code optimizer for a multiengine microprocessor | — | 2019-01-29 |
| 10146576 | Method for executing multithreaded instructions grouped into blocks | — | 2018-12-04 |
| 10042643 | Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor | — | 2018-08-07 |
| 10013254 | Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric | Karthikeyan Avudaiyappan | 2018-07-03 |
| 9990200 | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines | — | 2018-06-05 |
| 9965281 | Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer | — | 2018-05-08 |
| 9934072 | Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines | — | 2018-04-03 |
| 9934042 | Method for dependency broadcasting through a block organized source view data structure | — | 2018-04-03 |
| 9921850 | Instruction sequence buffer to enhance branch prediction efficiency | — | 2018-03-20 |
| 9921845 | Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines | — | 2018-03-20 |
| 9891915 | Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits | Ravishankar Rao | 2018-02-13 |