VT

Vipin Tiwari

ST Silicon Storage Technology: 96 patents #5 of 239Top 3%
VL Virage Logic: 5 patents #11 of 67Top 20%
University of California: 4 patents #2,189 of 18,278Top 15%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
Samsung: 1 patents #49,284 of 75,807Top 70%
🗺 California: #2,120 of 386,348 inventorsTop 1%
Overall (All Time): #13,564 of 4,157,543Top 1%
103
Patents All Time

Issued Patents All Time

Showing 76–100 of 103 patents

Patent #TitleCo-InventorsDate
10600484 System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory Nhan Do, Hieu Van Tran 2020-03-24
10586598 System and method for implementing inference engine by optimizing programming operation Nhan Do 2020-03-10
10580492 System and method for implementing configurable convoluted neural networks with flash memories Nhan Do 2020-03-03
10580491 System and method for managing peak power demand and noise in non-volatile memory array Hieu Van Tran, Nhan Do, Mark Reiten 2020-03-03
10534554 Anti-hacking mechanisms for flash memory device Hieu Van Tran, Nhan Do 2020-01-14
10522226 Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Nhan Do 2019-12-31
10515694 System and method for storing multibit data in non-volatile memory Nhan Do, Hieu Van Tran 2019-12-24
10460811 Array of three-gate flash memory cells with individual memory cell read, program and erase Hieu Van Tran, Nhan Do 2019-10-29
10446246 Method and apparatus for data refresh for analog non-volatile memory in deep learning neural network Hieu Van Tran, Nhan Do 2019-10-15
10388389 Flash memory array with individual memory cell read, program and erase Xinjie Guo, Farnood Merrikh Bayat, Dmitri Strukov, Nhan Do, Hieu Van Tran 2019-08-20
10381088 System and method for generating random numbers based on non-volatile memory cell array entropy Mark Reiten 2019-08-13
10340010 Method and apparatus for configuring array columns and rows for accessing flash memory cells Hieu Van Tran, Anh Ly, Thuan Vu, Nhan Do 2019-07-02
10311958 Array of three-gate flash memory cells with individual memory cell read, program and erase Hieu Van Tran, Nhan Do 2019-06-04
10283206 High speed sensing for advanced nanometer flash memory device Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen 2019-05-07
10275697 Method for automatically triggering data share event between sender device and receiver device Ritesh Kumar Sinha, Santosh Pallav SAHU, Manoj Kumar, Tasleem ARIF 2019-04-30
10269432 Method and apparatus for configuring array columns and rows for accessing flash memory cells Hieu Van Tran, Anh Ly, Thuan Vu, Nhan Do 2019-04-23
10269440 Flash memory array with individual memory cell read, program and erase Xinjie Guo, Farnood Merrikh Bayat, Dmitri Strukov, Nhan Do, Hieu Van Tran 2019-04-23
10249375 Flash memory array with individual memory cell read, program and erase Xinjie Guo, Farnood Merrikh Bayat, Dmitri Strukov, Nhan Do, Hieu Van Tran 2019-04-02
9601500 Array of non-volatile memory cells with ROM cells Jinho Kim, Nhan Do, Xian Liu, Xiaozhou Qian, Ning Bai +1 more 2017-03-21
9570592 Method of forming split gate memory cells with 5 volt logic devices Nhan Do 2017-02-14
9286982 Flash memory system with EEPROM functionality Hieu Van Tran, Hung Quoc Nguyen, Nhan Do 2016-03-15
8975131 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer Nhan Do, Hieu Van Tran, Xian Liu 2015-03-10
8004310 Power supply regulation 2011-08-23
7747425 System and method for peak current modeling for an IC design Manish Bhatia, Abhijit Ray 2010-06-29
7549136 System and method for approximating intrinsic capacitance of an IC block 2009-06-16