Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9762919 | Chroma cache architecture in block processing pipelines | Guy Cote, Joseph P. Bratt, Timothy J. Millet, Joseph Cheng | 2017-09-12 |
| 7903684 | Communications architecture for transmission of data between memory bank caches and ports | Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2011-03-08 |
| 7746798 | Method and system for integrating packet type information with synchronization symbols | Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2010-06-29 |
| 7340558 | Multisection memory bank system | Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2008-03-04 |
| 7257129 | Memory architecture with multiple serial communications ports | Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2007-08-14 |
| 7154905 | Method and system for nesting of communications packets | Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2006-12-26 |
| 7113507 | Method and system for communicating control information via out-of-band symbols | Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2006-09-26 |
| 6976201 | Method and system for host handling of communications errors | Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2005-12-13 |
| 6771192 | Method and system for DC-balancing at the physical layer | Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong | 2004-08-03 |
| 5956756 | Virtual address to physical address translation of pages with unknown and variable sizes | Yousef A. Khalidi, Glen Anderson, Stephen A. Chessin, Charles E. Narad, Madhusudhan Talluri | 1999-09-21 |
| 5771368 | Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers | Robert F. Cmelik, Edmund J. Kelly | 1998-06-23 |
| 5479627 | Virtual address to physical address translation cache that supports multiple page sizes | Yousef A. Khalidi, Glen Anderson, Stephen A. Chessin, Charles E. Narad, Madhusudhan Talluri | 1995-12-26 |
| 5465337 | Method and apparatus for a memory management unit supporting multiple page sizes | — | 1995-11-07 |
| 5430864 | Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size | Michael L. Powell, Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly | 1995-07-04 |
| 5210839 | Method and apparatus for providing a memory address from a computer instruction using a mask register | Michael L. Powell, Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly | 1993-05-11 |