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Chroma cache architecture in block processing pipelines |
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Communications architecture for transmission of data between memory bank caches and ports |
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Method and system for integrating packet type information with synchronization symbols |
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2010-06-29 |
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Multisection memory bank system |
Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong |
2008-03-04 |
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Memory architecture with multiple serial communications ports |
Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong |
2007-08-14 |
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Yeshik Shin, David D. Lee, Deog-Kyoon Jeong |
2006-12-26 |
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2006-09-26 |
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Yeshik Shin, David D. Lee, Deog-Kyoon Jeong |
2005-12-13 |
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2004-08-03 |
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Virtual address to physical address translation of pages with unknown and variable sizes |
Yousef A. Khalidi, Glen Anderson, Stephen A. Chessin, Charles E. Narad, Madhusudhan Talluri |
1999-09-21 |
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Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers |
Robert F. Cmelik, Edmund J. Kelly |
1998-06-23 |
| 5479627 |
Virtual address to physical address translation cache that supports multiple page sizes |
Yousef A. Khalidi, Glen Anderson, Stephen A. Chessin, Charles E. Narad, Madhusudhan Talluri |
1995-12-26 |
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Method and apparatus for a memory management unit supporting multiple page sizes |
— |
1995-11-07 |
| 5430864 |
Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size |
Michael L. Powell, Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly |
1995-07-04 |
| 5210839 |
Method and apparatus for providing a memory address from a computer instruction using a mask register |
Michael L. Powell, Robert F. Cmelik, David R. Ditzel, Edmund J. Kelly |
1993-05-11 |
