Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5978878 | Selective latency reduction in bridge circuit between two busses | — | 1999-11-02 |
| 5941970 | Address/data queuing arrangement and method for providing high data through-put across bus bridge | — | 1999-08-24 |
| 5894581 | Method for reducing control store space in a VLSI central processor | Wilbur L. Stewart, Richard L. Demers, Lowell D. McCulley | 1999-04-13 |
| 5644761 | Basic operations synchronization and local mode controller in a VLSI central processor | Ronald W. Yoder, William A. Shelly, Russell W. Guenthner, Richard L. Demers | 1997-07-01 |
| 5568622 | Method and apparatus for minimizing the number of control words in a brom control store of a microprogrammed central processor | Wilbur L. Stewart, Richard L. Demers | 1996-10-22 |
| 5557737 | Automated safestore stack generation and recovery in a fault tolerant central processor | John E. Wilhite | 1996-09-17 |
| 5553232 | Automated safestore stack generation and move in a fault tolerant central processor | John E. Wilhite | 1996-09-03 |
| 5515529 | Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count | William A. Shelly, Donald C. Boothroyd | 1996-05-07 |
| 5507000 | Sharing of register stack by two execution units in a central processor | Wilbur L. Stewart, Richard L. Demers, Jeffrey David Weintraub | 1996-04-09 |
| 5495579 | Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count | William A. Shelly, Donald C. Boothroyd | 1996-02-27 |
| 5367699 | Central processing unit incorporation selectable, precisa ratio, speed of execution derating | Russell W. Guenthner, Leonard Rabins | 1994-11-22 |
| 5276862 | Safestore frame implementation in a central processor | Lowell D. McCulley, Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, William A. Shelly +1 more | 1994-01-04 |
| 5263034 | Error detection in the basic processing unit of a VLSI central processor | Russell W. Guenthner, Clinton B. Eckard, Leonard Rabins, William A. Shelly, David Scott Edwards +1 more | 1993-11-16 |
| 5251321 | Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit | Donald C. Boothroyd, Clinton B. Eckard, William A. Shelly, Ronald W. Yoder | 1993-10-05 |
| 5195101 | Efficient error detection in a VLSI central processing unit | Russell W. Guenthner, Bruce E. Flocken | 1993-03-16 |
| 4831622 | Apparatus for forcing a reload from main memory upon cache memory error | Marion G. Porter, Marvin K. Webster | 1989-05-16 |
| 4424576 | Maintenance panel for communicating with an automated maintenance system | Robert J. Koegel | 1984-01-03 |
| 4405978 | Microprocessor based computer terminal | Steve King | 1983-09-20 |
| 4363108 | Low cost programmable video computer terminal | Steve King | 1982-12-07 |
| 4334289 | Apparatus for recording the order of usage of locations in memory | Richard J. Fisher | 1982-06-08 |
| 4322795 | Cache memory utilizing selective clearing and least recently used updating | Richard J. Fisher | 1982-03-30 |
| 4308615 | Microprocessor based maintenance system | Robert J. Koegel, Terry L. Davis | 1981-12-29 |
| 4298935 | Interface circuit for coupling an automated maintenance system to a CPU | Robert J. Koegel | 1981-11-03 |