Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11212625 | Adaptive noise cancelling of bone conducted noise in the mechanical domain | — | 2021-12-28 |
| 9466677 | Semiconductor structure including guard ring | Matthias Stecher | 2016-10-11 |
| 9431379 | Signal transmission arrangement | Jens-Peer Stengl, Uwe Wahl | 2016-08-30 |
| 9048019 | Semiconductor structure including guard ring | Matthias Stecher | 2015-06-02 |
| 8970000 | Signal transmission arrangement | Jens-Peer Stengl, Uwe Wahl | 2015-03-03 |
| 8823385 | Detection of pre-catastrophic, stress induced leakage current conditions for dielectric layers | — | 2014-09-02 |
| 8716832 | Semiconductor structure including guard ring | — | 2014-05-06 |
| 8620444 | Implant sensor and control | Martin Zimmerling, Ingeborg Hochmair, Erwin Hochmair, Werner Lindenthaler, Peter Nopp +3 more | 2013-12-31 |
| 8571673 | Energy saving silent mode for hearing implant systems | Martin Stoffaneller | 2013-10-29 |
| 8410575 | High voltage semiconductor devices and methods of forming the same | Uwe Wahl | 2013-04-02 |
| 7894240 | Method and apparatus for reducing charge trapping in high-k dielectric material | Michael Beck, Peter Lahnor, Roland Thewes | 2011-02-22 |
| 7782074 | System that detects damage in adjacent dice | — | 2010-08-24 |
| 7772039 | Procedure for arranging chips of a first substrate on a second substrate | — | 2010-08-10 |
| 7704853 | Method for the elimination of the effects of defects on wafers | Nikolaos Hatzopoulos | 2010-04-27 |
| 7652493 | Test arrangement having chips of a first substrate on a second substrate and chips of the second substrate on a third substrate | — | 2010-01-26 |
| 7550986 | Semiconductor wafer having a dielectric reliability test structure, integrated circuit product and test method | — | 2009-06-23 |
| 7403026 | Electronic switching circuit, switching circuit test arrangement and method for determining the operativeness of an electronic switching circuit | Thomas Pompl | 2008-07-22 |
| 6566271 | Method of producing a semiconductor surface covered with fluorine | Alexander Gschwandtner, Gudrun Innertsberger, Andreas Grassl, Barbara Fröschle, Alexander Mattheus | 2003-05-20 |
| 6433387 | Lateral bipolar transistor | — | 2002-08-13 |
| 6404034 | CMOS circuit with all-around dielectrically insulated source-drain regions | Dietrich Widmann | 2002-06-11 |
| 6239478 | Semiconductor structure for a MOS transistor | Udo Schwalke | 2001-05-29 |
| 6157060 | High density integrated semiconductor memory and method for producing the memory | — | 2000-12-05 |
| 6124156 | Process for manufacturing a CMOS circuit with all-around dielectrically insulated source-drain regions | Dietrich Widmann | 2000-09-26 |
| 6090665 | Method of producing the source regions of a flash EEPROM memory cell array | — | 2000-07-18 |
| 6027972 | Method for producing very small structural widths on a semiconductor substrate | — | 2000-02-22 |