DJ

Deog-Kyoon Jeong

SF Seoul National University R&Db Foundation: 51 patents #1 of 2,771Top 1%
SH Sk Hynix: 42 patents #93 of 4,849Top 2%
SI Silicon Image: 42 patents #1 of 173Top 1%
Samsung: 12 patents #11,258 of 75,807Top 15%
GS Gct Semiconductor: 12 patents #5 of 39Top 15%
Oracle: 8 patents #1,503 of 14,854Top 15%
UN Unknown: 3 patents #7,366 of 83,584Top 9%
GC Goldstar Electron Co.: 1 patents #72 of 188Top 40%
LC Lg Semicon Co.: 1 patents #258 of 547Top 50%
SF Seoul National University Industry Foundation: 1 patents #226 of 804Top 30%
UN Unidisplay: 1 patents #5 of 16Top 35%
KI Korea Electronics Technology Institute: 1 patents #338 of 614Top 60%
📍 Seoul, CA: #44 of 604 inventorsTop 8%
Overall (All Time): #8,972 of 4,157,543Top 1%
126
Patents All Time

Issued Patents All Time

Showing 51–75 of 126 patents

Patent #TitleCo-InventorsDate
8829969 Level-down shifter Moon-Sang Hwang, Won-Jun Choe, Hyun Chang Kim 2014-09-09
8729937 Coarse lock detector Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi 2014-05-20
8587355 Coarse lock detector and delay-locked loop including the same Moon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi 2013-11-19
8289314 Method of modulating/demodulating a signal, apparatus for performing the method and display apparatus having the apparatus Weon Jun Choe, Ah-Reum Kim, Kyo Jin Choo, Do Hwan Oh, Hee Soo Song 2012-10-16
8195855 Bi-directional multi-drop bus memory system Suhwan Kim, Woo Yeol SHIN, Dong-Hyuk Lim, Ic-Su Oh 2012-06-05
8106714 Adjustable capacitor, digitally controlled oscillator, and all-digital phase locked loop Do Hwan Oh, Kyo Jin Choo 2012-01-31
7973578 Time-to-digital converter and all-digital phase-locked loop Do Hwan Oh, Kyo Jin Choo 2011-07-05
7903684 Communications architecture for transmission of data between memory bank caches and ports Dongyun Lee, Yeshik Shin, David D. Lee, Shing Kong 2011-03-08
7746798 Method and system for integrating packet type information with synchronization symbols Yeshik Shin, David D. Lee, Shing Kong 2010-06-29
7627044 Clock-edge modulated serial link with DC-balance control Gyudong Kim, Won-Jun Choe, Jaeha Kim, Bong-Joon Lee, Min-Kyu Kim 2009-12-01
7602253 Adaptive bandwidth phase locked loop with feedforward divider Jaeha Kim 2009-10-13
7551909 CMOS transceiver with dual current path VCO Yongsam Moon, Young-soo Park 2009-06-23
7519138 Method and apparatus for data recovery in a digital data stream using data eye tracking Sang Hyun Lee 2009-04-14
7495590 Method of compensating channel offset voltage for column driver and column driver for LCD implemented thereof Won-Jun Choe 2009-02-24
7409031 Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization Bong-Joon Lee, Moon-Sang Hwang, Sang Hyun Lee 2008-08-05
7340558 Multisection memory bank system Dongyun Lee, Yeshik Shin, David D. Lee, Shing Kong 2008-03-04
7315598 Data recovery using data eye tracking Sang Hyun Lee 2008-01-01
7257129 Memory architecture with multiple serial communications ports Dongyun Lee, Yeshik Shin, David D. Lee, Shing Kong 2007-08-14
7203260 Tracked 3X oversampling receiver Yongsam Moon, Gijung Ahn 2007-04-10
7154905 Method and system for nesting of communications packets Yeshik Shin, David D. Lee, Shing Kong 2006-12-26
7113507 Method and system for communicating control information via out-of-band symbols Yeshik Shin, David D. Lee, Shing Kong 2006-09-26
7102446 Phase lock loop with coarse control loop having frequency lock detector and device including same Hyung Rok Lee, Moon-Sang Hwang, Sang Hyun Lee, Bong-Joon Lee 2006-09-05
7039121 Method and system for transition-controlled selective block inversion communications Yeshik Shin, David D. Lee 2006-05-02
7035351 Automatic gain control loop apparatus Joonbae Park, Wonchan Kim, Kyeongho Lee 2006-04-25
6976201 Method and system for host handling of communications errors Yeshik Shin, David D. Lee, Shing Kong 2005-12-13