Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8686507 | System and method for I/O ESD protection with floating and/or biased polysilicon regions | Min-Chie Jeng, Chin Chang Liao, Jun Cheng Huang | 2014-04-01 |
| 8319286 | System and method for input pin ESD protection with floating and/or biased polysilicon regions | Min-Chie Jeng, Chin Chang Liao, Jun Cheng Huang | 2012-11-27 |
| 8283726 | System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors | Min-Chie Jeng, Chin Chang Liao, Jun Cheng Huang | 2012-10-09 |
| 7642602 | System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors | Min-Chie Jeng, Chin Chang Liao, Jun Cheng Huang | 2010-01-05 |